Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un

Research and Design of a Routing Protocol in Large-Scale Wireless Sensor Networks

无线传感器网络，作为全球未来十大技术之一，集成了传感器技术、嵌入式计算技术、分布式信息处理和自组织网技术，可实时感知、采集、处理、传输网络分布区域内的各种信息数据，在军事国防、生物医疗、环境监测、抢险救灾、防恐反恐、危险区域远程控制等领域具有十分广阔的应用前景。 本文研究分析了无线传感器网络的已有路由协议，并针对大规模的无线传感器网络设计了一种树状路由协议，它根据节点地址信息来形成路由，从而简化了复杂繁冗的路由表查找和维护，节省了不必要的开销，提高了路由效率，实现了快速有效的数据传输。 为支持此路由协议本文提出了一种自适应动态地址分配算——ADAR（AdaptiveDynamicAddre...As one of the ten high technologies in the future, wireless sensor network, which is the integration of micro-sensors, embedded computing, modern network and Ad Hoc technologies, can apperceive, collect, process and transmit various information data within the region. It can be used in military defense, biomedical, environmental monitoring, disaster relief, counter-terrorism, remote control of haz...学位：工学硕士院系专业：信息科学与技术学院通信工程系_通信与信息系统学号：2332007115216

Real time vision by FPGA implemented CNNs

In order to get real time image processing for mobile robot vision, we propose to use a discrete time Cellular Neural Network implementation by a convolutional structure on Altera FPGA using VHDL language. We obtain at least 9 times faster processing than other emulations for the same problem

Real time computer vision by means of CNNs on FPGAs

In previous works [1, 2] we developed a visual servoing platform using C language to extract the required information from the images, the necessary time to process the images don't allow us to achieve a real time operation. In order to get real time image processing we proposed to use Discrete time Cellular Neural Networks [10, 11]. In this paper we report on CNN emulation on Altera FPGA using VHDL language

"Optimized Cellular Neural Network Universal Machine Emulation on FPGA

An FPGA architecture to emulate a single-layer Cellular Neural Network - Universal Machine (CNN-UM) is proposed. It is based on a fast realization of the CNN convolution operation on the parallel hardware of the FPGA. The setup is capable of performing a CNN iteration over a 30×30 pixel image in less than 30 μs. Moreover, this platform has been used to realize the visual system of an autonomous mobile robot. © 2007 IEEE

SiD Letter of Intent

Letter of intent describing SiD (Silicon Detector) for consideration by the International Linear Collider IDAG panel. This detector concept is founded on the use of silicon detectors for vertexing, tracking, and electromagnetic calorimetry. The detector has been cost-optimized as a general-purpose detector for a 500 GeV electron-positron linear collider.Letter of intent describing SiD (Silicon Detector) for consideration by the International Linear Collider IDAG panel. This detector concept is founded on the use of silicon detectors for vertexing, tracking, and electromagnetic calorimetry. The detector has been cost-optimized as a general-purpose detector for a 500 GeV electron-positron linear collider